The present invention relates to a highly integrated semiconductor device, and more particularly, to a semiconductor memory device including a clock data recovery (CDR) circuit for recovering signals and data distorted during high-speed processing.
Semiconductor memory devices are used for storing data in various systems such as a system composed of a plurality of semiconductor devices. When a data processing device, such as a central processing unit (CPU), requests or sends data, a semiconductor memory device outputs or stores the data based on address information received from the data processing device.
As the operating speed of a semiconductor device system increases owing to the advance of semiconductor integrated circuit technology, the semiconductor device system requires high-speed semiconductor memory devices capable of rapidly outputting and storing data. For high-speed and stable operations of a semiconductor memory device, circuits of the semiconductor memory device need to be operated at a high speed. That is, the circuits of the semiconductor memory device need to process signals or data rapidly and transfer the signals or data at a high speed.
As the operating speed of semiconductor memory devices need to be high for being used in high-speed systems, the signal/data transmission speed of interfaces is also required to be high. A clock data recovery (CDR) method has been developed to prevent malfunctions or instable operations of a semiconductor memory device caused by noises, interferences, and distortions of signals and data.
That is, a recent semiconductor memory device includes a CDR circuit for reliably transferring signals and data at a high speed. CDR technology is used in most high-speed systems for recovering original data and clock signals from data and clock signals distorted or changed during transmission.
In a semiconductor memory device, transmission of data and clock signals can be delayed due to various reasons. In this case, the semiconductor memory device cannot normally operate according to the data and clock signals, and thus the possibility of malfunction of the semiconductor memory device increases. To solve these problems, circuits of the semiconductor memory device can be operated according to an inner clock produced corresponding to an external reference clock. When the inner clock is not in phase with the external reference clock, the phase difference is detected and reported to the circuits so as to allow the circuits to change the phase of the inner clock in response to the reported phase difference or operate in consideration of the phase difference.
The above-described operation can be performed using a CDR circuit. For this, the CDR circuit includes a phase comparator and a filter. The phase comparator detects a difference between the external reference clock and the inner clock, and the detection result is output through the filter.
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device including CDR circuits.
Referring to FIG. 1, for example, the semiconductor memory device includes first to thirty second data pads DQ0 to D31, and first to thirty second CDR circuits 120_0 to 120_31 respectively connected to the first to thirty second data pads DQ0 to D31. The first CDR circuit 120_0 includes a receiver 122_0, a sampling unit 124_0, a delay unit 128_0, and a phase detection unit 126_0. The other CDR circuits 120_1 to 120_31 have the same elements. Thus, descriptions of the other CDR circuits 120_1 to 120_31 will be omitted.
Each of the first to thirty second CDR circuits 120_0 to 120_31 connected to the first to thirty second data pads DQ0 to D31 can recover clock data with no aid from other devices. This will now be described using the first CDR circuit 120_0 as an example. The receiver 122_0 receives a signal through the first data pad DQ0 and transfers the signal to the sampling unit 124_0. First, the sampling unit 124_0 transfers the signal to the phase detection unit 126_0 according to a receiving reference clock RX_CLK. The phase detection unit 126_0 detects transition time points of signals transferred from the sampling unit 124_0 (that is, time points at which successively transferred signals change from a logic high level to a logic low level, or from a logic low level to a logic high level). Then, the phase detection unit 126_0 calculates a delay value so as to place the transition time points on the centers of rising and falling edges of the receiving reference clock RX_CLK. The delay unit 128_0 delays the receiving reference clock RX_CLK according to the delay value so as to adjust the phase of the receiving reference clock RX_CLK. Then, the sampling unit 124_0 transfers signals transferred from the receiver 122_0 to an inner unit of the semiconductor memory device according to the phase-adjusted receiving reference clock RX_CLK. Since the phase of the receiving reference clock RX_CLK can be adjusted as described above, signal input/output errors can be prevented when the semiconductor memory device receives and transfers signals at a high speed.
Each of the first to thirty second CDR circuits 120_0 to 120_31 connected to the first to thirty second data pads DQ0 to D31 includes a clock generator (not shown). The clock generator generates a receiving reference clock RX_CLK that is used for determining the time for recognizing input signals.
Since the first to thirty second data pads DQ0 to D31 can have different data transmission delay levels, the first to thirty second CDR circuits 120_0 to 120_31 are connected to the first to thirty second data pads DQ0 to D31, respectively. However, the first to thirty second CDR circuits 120_0 to 120_31 occupy a large area of the semiconductor memory device. Therefore, the number of data transmission channels of the semiconductor memory device may be limited, or the power consumption of the semiconductor memory device may be increased due to the CDR operation.